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PARAMETER MEASUREMENT INFORMATION

50%

LATCH

GND

10%

90%

GND

Propagation Delay (xVPP)

50%

LATCH

GND

10%

90%

GND

Propagation Delay (xVCC)

10%

90%

GND

Rise/Fall Time (xVPP)

10%

90%

GND

Rise/Fall Time (xVCC)

50%

GND

10%

90%

GND

Turnon/off Time (xVCC)

xVPP

VOLTAGE WAVEFORMS

LOAD CIRCUIT (xVPP)

xVCC

50%

LATCH

GND

10%

90%

GND

Turnon/off Time (xVPP)

LOAD CIRCUIT (xVCC)

LATCH

D10

D9

D8

D7

D6

D5

D4

D3

D2

DATA

LATCH

CLOCK

D1

D0

Data Setup Time

Data Hold Time

Latch Delay Time

Clock Delay Time

TPS2220A, TPS2223A

TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

Figure 1. Test Circuits and Voltage Waveforms

NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next

positive edge of the clock. For definition of D0 to D10, see the control logic table.

Figure 2. Serial-Interface Timing for TPS2226A

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