TSB12LV22

OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER

SLLS290A − JULY 1998 − REVISED NOVEMBER 1998

7

POST OFFICE BOX 655303

OHCI-Lynx controller programming model (continued)

A bit description table is typically included that indicates bit field names, a detailed field description, and field

access tags. The field access tags are described in Table 2.

Table 2. Bit Field Access Tag Descriptions

ACCESS TAG

NAME

MEANING

r

read

Field may be read by software.

w

write

Field may be written by software to any value.

s

set

Field may be set by a write of one. Writes of zero have no effect.

c

clear

Field may be cleared by a write of one. Writes of zero have no effect.

u

update

Field may be autonomously updated by the OHCI-Lynx.

PCI configuration registers

The OHCI-Lynx configuration header is compliant with the PCI Specification as a standard header.Table 3

illustrates the PCI configuration header which includes both the predefined portion of the configuration space

and the user definable registers. The registers that are labeled Reserved are read only returning zero when

read, and are not applicable to the OHCI-Lynx design, or have been reserved by the PCI specification for future

use.

Table 3. PCI Configuration Register Map

REGISTER NAME

OFFSET

Device ID

Vendor ID

00h

Status

Command

04h

Class Code

Revision ID

08h

BIST

Header type

Latency timer

Cache lLine size

0Ch

Open HCI registers base address

10h

TI extension registers base address

14h

Reserved

18h

Reserved

1Ch

Reserved

20h

Reserved

24h

Reserved

28h

Subsystem ID

Subsystem vendor ID

2Ch

Reserved

30h

Reserved

Capabilites pPointer

34h

Reserved

38h

Max latency

Min grant

Interrupt pin

Interrupt line

3Ch

PCI OHCI Control Register

40h

Power management capabilities

Next item Pointer

Capability ID

44h

PM Data

PMCSR_BSE

Power management CSR

48h

Reserved

4C−F2h

Link_Enhancements register

F4h

Subsytem ID alias

Subsystem vendor ID alias

F8h

GPIO3

GPIO2

GPIO1

GPIO0

FCh