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DAC7731EC1K датащи(PDF) 11 Page - Burr-Brown (TI) |
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DAC7731EC1K датащи(HTML) 11 Page - Burr-Brown (TI) |
11 / 17 page DAC7731 11 SBAS249 www.ti.com V CC REF OUT REF IN REFADJ V REF R OFFSET AGND RFB2 RFB1 SJ V OUT V DD V SS REFEN RSTSEL SCLK CS SDO SDI LDAC RST NC TEST DGND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DAC7731 1 µF 0.1 µF V CC 1 µF 0.1 µF V DD Control/Data Bus 1 µF0.1µF V SS (–10V to +10V) FIGURE 4. Basic Operation: VOUT = –10V to +10V. ANALOG OUTPUTS The output amplifier can swing to within 1.4V of the supply rails, specified over the –40 °C to +85°C temperature range. This allows for a ±10V DAC voltage output operation from ±12V supplies with a typical 5% tolerance. When the DAC7731 is configured for a unipolar, 0V to 10V output, a negative voltage supply is required. This is due to internal biasing of the output stage. Please refer to the “Electrical Characteristics” table for more information. The minimum and maximum voltage output values are de- pendent upon the output configuration implemented and reference voltage applied to the DAC7731. Please note that VSS (the negative power supply) must be in the range of –4.75V to –15.75V for unipolar operation. The voltage on VSS sets several bias points within the converter and is required in all modes of operation. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not ensured. REFERENCE INPUTS The DAC7731 provides a built-in +10V voltage reference and on-chip buffer to allow external component reference drive. To use the internal reference, REFEN must be LOW, enabling the reference circuitry of the DAC7731 (as shown in Table I) and the REFOUT pin must be connected to REFIN. This is the input to the on-chip reference buffer. The buffer’s output is provided at the VREF pin. In this configuration, VREF is used to setup the DAC7731 output amplifier into one of three voltage output modes as discussed earlier. VREF can also be used to drive other system components requiring an external reference. The internal reference of the DAC7731 can be disabled when use of an external reference is desired. When using an external reference, the reference input, REFIN, can be any voltage between 4.75V (or VSS + 14V, whichever is greater) and VCC – 1.4V. REFSEL ACTION 1 Internal Reference disabled; REFOUT = High Impedance 0 Internal Reference enabled; REFOUT = +10V TABLE I. REFEN Action. DIGITAL INTERFACE Table II shows the input data format for the DAC7731 and Table III illustrates the basic control logic of the device. The serial interface consists of a chip select input (CS), serial data clock input (SCLK), serial data input (SDI), serial data output (SDO), and load control input (LDAC). An asynchronous reset input (RST), which is active LOW, is provided to simplify start- up conditions, periodic resets, or emergency resets to a known state, depending on the status of the reset select (RSTSEL) signal. Please refer to the "DAC Reset" section for additional information regarding the reset operation. CONTROL STATUS COMMAND CS RST RSTSEL LDAC SCLK ACTION H H X X X Shift Register is disabled on the serial bus. Enable SDO pin from High Impedance; L H X X X enables shift operation and I/O bus (SCLK, SDI, SDO). LH X X ↑ Serial Data Shifted into Input Register ↑ H X X L Serial Data Shifted into Input Register(1) XH X ↑ X Data in Input Register is Loaded into DAC Register. X L H X X Resets Input and DAC Registers to mid-scale. X L L X X Resets Input and DAC Registers to min-scale. NOTE: (1) In order to avoid unwanted shifting of the input register by an additional bit, care must be taken that a rising edge on CS only occurs when SCLK is HIGH. TABLE III. DAC7731 Logic Truth Table. ANALOG OUTPUT TABLE II. DAC7731 Data Format. DIGITAL INPUT Unipolar Configuration Bipolar Configuration Unipolar Straight Binary Bipolar Offset Binary 0x0000 Zero (0V) –Full-Scale (–VREF or –VREF/2) 0x0001 Zero + 1LSB –Full-Scale + 1LSB :: : 0x8000 1/2 Full-Scale Bipolar Zero 0x8001 1/2 Full-Scale + 1LSB Bipolar Zero + 1LSB :: : 0xFFFF Full-Scale (VREF – 1LSB) +Full-Scale (+VREF – 1LSB or +VREF/2 – 1LSB) The DAC code is provided via a 16-bit serial interface, as shown in Table II. The digital input word makes up the digital code to be loaded into the data input register of the device. A typical data transfer and DAC output update takes place as follows: Once CS is active (LOW), the DAC7731 is enabled on the serial bus and the 16-bit serial data transfer can begin. The serial data is shifted into the device on each rising SCLK edge until all 16 bits are transferred (1 bit per 1 rising SCLK edge). Once received, the data in the input register is loaded into the DAC register upon reception of a rising edge on the LDAC input (load command). This action updates the analog output, VOUT, to the desired voltage specified by the digital input word. A rising edge |
Аналогичный номер детали - DAC7731EC1K |
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Аналогичное описание - DAC7731EC1K |
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