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9ZXL1231AKLF датащи(PDF) 4 Page - Integrated Device Technology |
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9ZXL1231AKLF датащи(HTML) 4 Page - Integrated Device Technology |
4 / 18 page 12-OUTPUT DB1200ZL 4 REVISION J 05/25/16 9ZXL1231 DATASHEET Pin Descriptions PIN # PIN NAME TYPE DESCRIPTION 1 VDDA PWR Power for the PLL core. 2 GNDA GND Ground pin for the PLL core. 3 NC N/A No Connection. 4 100M_133M# IN 3.3V Input to select operating frequency. See Functionality Table for Definition 5 HIBW_BYPM_LOBW# IN Trilevel input to select High BW, Bypass or Low BW mode. See PLL Operating Mode Table for Details. 6 CKPWRGD_PD# IN 3.3V Input notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode. 7 GND GND Ground pin. 8 VDDR PWR 3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. 9 DIF_IN IN HCSL True input 10 DIF_IN# IN HCSL Complementary Input 11 SMB_A0_tri IN SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9 SMBus Addresses. 12 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant 13 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 14 SMB_A1_tri IN SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9 SMBus Addresses. 15 DFB_OUT_NC# OUT Complementary half of differential feedback output, provides feedback signal to the PLL for synchronization with input clock to eliminate phase error. This pin should NOT be connected on the circuit board, the feedback is internal to the package. 16 DFB_OUT_NC OUT True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input clock to eliminate phase error. This pin should NOT be connected on the circuit board, the feedback is internal to the package. 17 DIF_0 OUT HCSL true clock output 18 DIF_0# OUT HCSL Complementary clock output 19 vOE0# IN Active low input for enabling DIF pair 0. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 20 vOE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 21 DIF_1 OUT HCSL true clock output 22 DIF_1# OUT HCSL Complementary clock output 23 GND GND Ground pin. 24 VDD PWR Power supply, nominal 3.3V 25 VDDIO PWR Power supply for differential outputs 26 DIF_2 OUT HCSL true clock output 27 DIF_2# OUT HCSL Complementary clock output 28 vOE2# IN Active low input for enabling DIF pair 2. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 29 vOE3# IN Active low input for enabling DIF pair 3. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 30 DIF_3 OUT HCSL true clock output 31 DIF_3# OUT HCSL Complementary clock output 32 VDDIO PWR Power supply for differential outputs 33 GND GND Ground pin. 34 DIF_4 OUT HCSL true clock output 35 DIF_4# OUT HCSL Complementary clock output 36 vOE4# IN Active low input for enabling DIF pair 4. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 37 vOE5# IN Active low input for enabling DIF pair 5. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs |
Аналогичный номер детали - 9ZXL1231AKLF |
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Аналогичное описание - 9ZXL1231AKLF |
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