12-OUTPUT DB1200ZL DERIVATIVE WITH INTEGRATED 85Ω TERMINATIONS 2

REVISION B 11/20/15

9ZXL1251 DATASHEET

Pin Configuration

Power Management Table

Functionality at Power-up (PLL mode)

Power Connections

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VDDA 1

48 GND

GNDA 2

47 DIF_7#

NC 3

46 DIF_7

^100M_133M# 4

45 vOE7#

^vHIBW_BYPM_LOBW# 5

44 vOE6#

CKPWRGD_PD# 6

43 DIF_6#

GND 7

42 DIF_6

VDDR 8

41 GND

DIF_IN 9

40 VDD

DIF_IN# 10

39 DIF_5#

vSMB_A0_tri 11

38 DIF_5

SMBDAT 12

37 vOE5#

SMBCLK 13

36 vOE4#

vSMB_A1_tri 14

35 DIF_4#

DFB_OUT_NC# 15

34 DIF_4

DFB_OUT_NC 16

33 GND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Note: Pins with ^ prefix have internal 120K pullup

Pins with v prefix have internal 120K pulldowm

Pins with ^v prefix have internal 120K pullup/pulldown (biased to VDD/2)

9ZXL1251

connect epad (pin 65)

to ground

9 x 9mm VFQFPN package

CKPWRGD_PD#

DIF_IN/

DIF_IN#

SMBus

EN bit

DIF(11:0)/

DIF(11:0)#

PLL STATE

IF NOT IN

BYPASS

MODE

0

X

X

Low/Low

OFF

0

Low/Low

ON

1

Running

ON

Running

1

100M_133M#

DIF_IN

MHz

DIF(11:0)

1

100.00

DIF_IN

0

133.33

DIF_IN

VDD

VDDIO

GND

12

Analog PLL

8

7

Analog Input

24,40,57

25,32,49,56

23,33,41,48,

58,65

DIF clocks

Pin Number

Description