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UC1846-SP датащи(PDF) 10 Page - Texas Instruments |
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UC1846-SP датащи(HTML) 10 Page - Texas Instruments |
10 / 29 page Ip D2 L1 V O D1 Current Mode Control PWM I SENSE 8 V SENSE – V IN Q 1 Q 2 Np Np R S + N S N S I S C1 – + 10 UC1846-SP SLUS871D – JANUARY 2009 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: UC1846-SP Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Feature Description (continued) The peak method of inductor current control functions by comparing the upslope of inductor current (or switch current) to a current program level set by the outer loop. The comparator turns the power switch off when the instantaneous current reaches the desired level. The current ramp is usually quite small compared to the programming level, especially when VIN is low. As a result, this method is extremely susceptible to noise. A noise spike is generated each time the switch turns on. A fraction of a volt coupled into the control circuit can cause it to turn off immediately, resulting in a sub-harmonic operating mode with much greater ripple. Circuit layout and bypassing are critically important to successful operation. The peak current mode control method is inherently unstable at duty ratios exceeding 0.5, resulting in sub- harmonic oscillation. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. A slope compensation must be added to the sensed current waveform or subtracted from the control voltage to ensure stability above a 50% duty cycle. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. The pulse width modulator (PWM) of UC1846-SP is limited to a maximum duty cycle of 50%, thus it can be used in topologies such as push-pull, half bridge, full bridge, forward, flyback configurations. Limiting PWM to 50% duty cycle ensures that for isolated or transformer based topologies. The transformer is allowed to reset and prevent saturation of the transformer core. Pulse-by-pulse symmetry correction (flux balancing) is inherent to current mode controllers and essential for the push-pull topology to prevent core saturation. Current limit control design has numerous advantages: 1. Current mode control provided peak switch current limiting – pulse by pulse current limit. 2. Control loop is simplified as one pole due to output inductor is pushed to higher frequency , thus a two pole system turns into two real poles. Thus system reduces to a first order system thus simplifies the control. 3. Multiple converter can be paralleled and allows equal current sharing amount the various converters. 4. Inherently provides for input voltage feed-forward as any perturbation in the input voltage will be reflected in the switch or inductor current. Since switch or inductor current is a direct control input, thus this perturbation is very rapidly corrected. 5. The error amplifier output (outer control loop) defines the level at which the primary current (inner loop) will regulate the pulse width, and output voltage. Figure 3. Push-Pull Converter Using Current Mode Control 7.3.1 Reference As highlighted in the Functional Block Diagram, UC1846-SP incorporates a 5.1-V internal reference regulator with ±10% set point variation over temperature. |
Аналогичный номер детали - UC1846-SP_16 |
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Аналогичное описание - UC1846-SP_16 |
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