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SL28PCIe25ALCT датащи(PDF) 8 Page - Silicon Laboratories |
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SL28PCIe25ALCT датащи(HTML) 8 Page - Silicon Laboratories |
8 / 17 page SL28PCIe25 DOC#: SP-AP-0776 (Rev. 0.2) Page 8 of 16 Byte 13: Control Register 13 Byte 14: Control Register 14 . PD# (Power down) Clarification The CKPWRGD/PD# pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Once CKPWRGD has been sampled HIGH by the clock chip, the pin assumes PD# functionality. The PD# pin is an asynchronous active LOW input used to shut off all clocks cleanly before shutting off power to the device. This signal is synchronized internally to the device before powering down the clock synthesizer. PD# is also an asynchronous input for powering up the system. When PD# is asserted LOW, clocks are driven to a LOW value and held before turning off the VCOs and the crystal oscillator. PD# (Power down) Assertion When PD is sampled HIGH by two consecutive rising edges of SRCC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held LOW. When PD mode is desired as the initial power on state, PD must be asserted HIGH in less than 10 s after asserting CKPWRGD. PD# Deassertion The power up latency is less than 1.8 ms. This is the time from the deassertion of the PD# pin or the ramping of the power supply until the time that stable clocks are generated from the clock chip. All differential outputs stopped in a three-state condition, resulting from power down are driven high in less than 300 s of PD# deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of each clock. Figure 2 is an example showing the relationship of clocks coming up. Bit @Pup Name Description 7 1 REF_Bit2 Drive Strength Control - Bit[2:0] , Note: Slew Rate REF Bit1 is located in Byte 6 Bit 5 Normal mode default ‘101’ Wireless Friendly Mode default to ‘111’ 61 REF_Bit0 5 1 RESERVED 4 1 RESERVED 3 1 RESERVED 2 1 RESERVED 1 0 RESERVED RESERVED 0 0 Wireless Friendly mode Wireless Friendly Mode 0 = Disabled, Default all single-ended clocks slew rate config bits to ‘101’ 1 = Enabled, Default all single-ended clocks slew rate config bits to ‘111’ Bit @Pup Name Description 7 1 RESERVED RESERVED 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 40 OTP_4 OTP_ID Idenification for programmed device 30 OTP_3 21 OTP_2 10 OTP_1 00 OTP_0 Table 4. Output Driver Status All Differential Clocks Clock Clock# PD# = 0 (Power down) Low Low |
Аналогичный номер детали - SL28PCIe25ALCT |
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Аналогичное описание - SL28PCIe25ALCT |
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