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AD9142A-M5375-EBZ датащи(PDF) 3 Page - Analog Devices

номер детали AD9142A-M5375-EBZ
подробное описание детали  Multiple chip synchronization
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9142A-M5375-EBZ датащи(HTML) 3 Page - Analog Devices

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AD9142A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 4
Functional Block Diagram .............................................................. 5
Specifications..................................................................................... 6
DC Specifications ......................................................................... 6
Digital Specifications ................................................................... 8
DAC Latency Specifications........................................................ 9
Latency Variation Specifications ................................................ 9
AC Specifications........................................................................ 10
Operating Speed Specifications................................................ 10
Absolute Maximum Ratings ..................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 15
Terminology .................................................................................... 20
Serial Port Operation ..................................................................... 21
Data Format ................................................................................ 21
Serial Port Pin Descriptions...................................................... 21
Serial Port Options..................................................................... 21
Data Interface.................................................................................. 23
LVDS Input Data Ports.............................................................. 23
Word Interface Mode................................................................. 23
Byte Interface Mode ................................................................... 23
Data Interface Configuration Options .................................... 23
DLL Interface Mode................................................................... 23
Parity ............................................................................................ 26
SED Operation............................................................................ 26
SED Example............................................................................... 27
Delay Line Interface Mode........................................................ 27
FIFO Operation .............................................................................. 29
Resetting the FIFO ..................................................................... 30
Serial Port Initiated FIFO Reset ............................................... 30
Frame Initiated FIFO Reset....................................................... 30
Digital Datapath.............................................................................. 32
Interpolation Filters ................................................................... 32
Digital Modulation..................................................................... 34
Datapath Configuration ............................................................ 35
Digital Quadrature Gain and Phase Adjustment................... 35
DC Offset Adjustment............................................................... 35
Inverse Sinc Filter....................................................................... 36
Input Signal Power Detection and Protection........................ 36
Transmit Enable Function......................................................... 37
Digital Function Configuration ............................................... 37
Multidevice Synchronization and Fixed Latency....................... 38
Very Small Inherent Latency Variation................................... 38
Further Reducing the Latency Variation................................. 38
Synchronization Implementation ............................................ 39
Synchronization Procedures..................................................... 39
Interrupt Request Operation ........................................................ 40
Interrupt Working Mechanism ................................................ 40
Interrupt Service Routine.......................................................... 40
Temperature Sensor ....................................................................... 41
DAC Input Clock Configurations ................................................ 42
Driving the DACCLK and REFCLK Inputs ........................... 42
Direct Clocking .......................................................................... 42
Clock Multiplication .................................................................. 42
PLL Settings ................................................................................ 43
Configuring the VCO Tuning Band ........................................ 43
Automatic VCO Band Select .................................................... 43
Manual VCO Band Select ......................................................... 43
PLL Enable Sequence................................................................. 43
Analog Outputs............................................................................... 44
Transmit DAC Operation.......................................................... 44
Interfacing to Modulators ......................................................... 45
Reducing LO Leakage and Unwanted Sidebands .................. 46
Example Start-Up Routine ............................................................ 47
Device Configuration and Start-Up Sequence 1.................... 47
Device Configuration and Start-Up Sequence 2.................... 47
Device Configuration Register Map and Description............... 49
SPI Configure Register .............................................................. 52
Power-Down Control Register ................................................. 52
Interrupt Enable0 Register........................................................ 52
Interrupt Enable1 Register........................................................ 53
Interrupt Flag0 Register............................................................. 53
Interrupt Flag1 Register............................................................. 53
Interrupt Select0 Register.......................................................... 54
Rev. A | Page 2 of 72


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