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X1228V14I-4.5A датащи(PDF) 11 Page - Xicor Inc.

номер детали X1228V14I-4.5A
подробное описание детали  Real Time Clock/Calendar/CPU Supervisor with EEPROM
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производитель  XICOR [Xicor Inc.]
домашняя страница  http://www.xicor.com
Logo XICOR - Xicor Inc.

X1228V14I-4.5A датащи(HTML) 11 Page - Xicor Inc.

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X1228
REV 1.3 3/24/04
Characteristics subject to change without notice.
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CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The clock/
control memory map has memory addresses from
0000h to 003Fh. The defined addresses are described
in the Table 1. Writing to and reading from the
undefined addresses are not recommended.
CCR access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read. The
read instruction latches all Clock registers into a buffer,
so an update of the clock does not change the time
being read. A sequential read of the CCR will not result
in the output of data from the memory array. At the end
of a read, the master supplies a stop condition to end
the operation and free the bus. After a read of the
CCR, the address remains at the previous address +1
so the user can execute a current address read of the
CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24 hour time selection bit. The enable
bits specify which registers to use in the comparison
between the Alarm and Real Time Registers. For
example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
Bit
Range
76
54321
0 (optional)
003F
Status
SR
BAT
AL1
AL0
0
0
RWEL
WEL
RTCF
01h
0037
RTC
(SRAM)
Y2K
0
0
Y2K21
Y2K20
Y2K13
0
0
Y2K10
19/20
20h
0036
DW
0
0
0
0
0
DY2
DY1
DY0
0-6
00h
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0-99
00h
0034
MO
0
0
0
G20
G13
G12
G11
G10
1-12
00h
0033
DT
0
0
D21
D20
D13
D12
D11
D10
1-31
00h
0032
HR
MIL
0
H21
H20
H13
H12
H11
H10
0-23
00h
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
00h
0030
SC
0
S22
S21
S20
S13
S12
S11
S10
0-59
00h


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