1998 Jul 08

2

Philips Semiconductors

Product specification

8-bit synchronous binary down counter

74HC/HCT40103

FEATURES

• Cascadable

• Synchronous or asynchronous preset

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT40103 are high-speed Si-gate CMOS

devices and are pin compatible with the “40103” of the

“4000B” series. They are specified in compliance with

JEDEC standard no. 7A.

The 74HC/HCT40103 consist each of an 8-bit

synchronous down counter with a single output which is

active when the internal count is zero. The “40103”

contains a single 8-bit binary counter and has control

inputs for enabling or disabling the clock (CP), for clearing

the counter to its maximum count, and for presetting the

counter either synchronously or asynchronously. All

control inputs and the terminal count output (TC) are

active-LOW logic.

In normal operation, the counter is decremented by one

count on each positive-going transition of the clock (CP).

Counting is inhibited when the terminal enable input (TE)

is HIGH. The terminal count output (TC) goes LOW when

the count reaches zero if TE is LOW, and remains LOW for

one full clock period.

When the synchronous preset enable input (PE) is LOW,

on the next positive-going clock transition regardless of the

state of TE. When the asynchronous preset enable input

asynchronously forced into the counter regardless of the

a single 8-bit binary word.

When the master reset input (MR) is LOW, the counter is

asynchronously cleared to its maximum count (decimal

255) regardless of the state of any other input. The

precedence relationship between control inputs is

indicated in the function table.

If all control inputs except TE are HIGH at the time of zero

count, the counters will jump to the maximum count, giving

a counting sequence of 256 clock pulses long.

The “40103” may be cascaded using the TE input and the

TC output, in either a synchronous or ripple mode.

QUICK REFERENCE DATA

Notes

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay CP to TC

30

30

ns

maximum clock frequency

32

31

MHz

input capacitance

3.5

3.5

pF

power dissipation capacitance per package

notes 1 and 2

24

27

pF