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74LVC16245ADL датащи(PDF) 2 Page - Integrated Circuit Systems |
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74LVC16245ADL датащи(HTML) 2 Page - Integrated Circuit Systems |
2 / 19 page 2003 Nov 25 2 Philips Semiconductors Product specification 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 74LVC16245A; 74LVCH16245A FEATURES • 5 V tolerant inputs/outputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • High-impedance when VCC =0V • All data inputs have bushold (74LVCH16245A only) • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. DESCRIPTION The 74LVC(H)16245A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 Volt. These features allow the use of these devices as a mixed 3.3 and 5 V environment. The 74LVC(H)16245A is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for direction control. nOE controls the outputs so that the buses are effectively isolated. This device can be used as two 8-bit transceivers or one 16-bit transceiver. The 74LVCH16245A bushold data inputs eliminates the need for external pull-up resistors to hold unused inputs. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay nAn to nBn; nBn to nAn CL = 50 pF; VCC = 3.3 V 2.2 ns CI input capacitance 5.0 pF CI/O input/output capacitance 10 pF CPD power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 30 pF |
Аналогичный номер детали - 74LVC16245ADL |
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Аналогичное описание - 74LVC16245ADL |
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