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GS9000CCTJ датащи(PDF) 3 Page - Gennum Corporation |
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GS9000CCTJ датащи(HTML) 3 Page - Gennum Corporation |
3 / 8 page 3 522 - 49 - 01 PD7 PD6 PD5 PD4 PD3 PD2 PD1 SDI SDI SCI SCI SS1 SS0 SSC (MSB) VSS SWF VSS HSYNC PD9 PD8 VSS GS9000C TOP VIEW VDD VDD SCE SWC PCLK PD0 VDD (LSB) 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 28 27 26 GS9000C PIN DESCRIPTIONS PIN NO. SYMBOL TYPE DESCRIPTION 1 HSYNC Output Horizontal Sync Output. CMOS (TTL compatible) output that toggles for each TRS detected. 2V SS Power Supply. Most negative power supply connection. 3 SWF Output Sync Error Warning Flag. CMOS (TTL compatible) active high output that indicates the preselected HSYNC Error Rate (HER). The HER is set with an RC time constant on the SWC input. 4V SS Power Supply. Most negative power supply connection. 5,6 SDI/SDI Inputs Differential, pseudo-ECL serial data inputs. ECL voltage levels with offset of 3.0V to 4.0V for operation up to 370MHz. See AC Electrical Characteristics Table for details. 7,8 SCI/SCI Inputs Differential, pseudo-ECL serial clock inputs. ECL voltage levels with offset of 3.0V to 4.0V for operation up to 370MHz. See AC Electrical Characteristics Table for details. 9,10 SS1/SS0 Output Standard Select Outputs. CMOS (TTL compatible) outputs used with the GS9005A Receiver in order to perform an automatic standards select function. These outputs are generated by a 2 bit internal binary counter which stops cycling when there is no CARRIER present at the GS9005A Receiver input or when a valid TRS is detected by the GS9000C. 11 SSC Input Standards Select Control. Analog input used to set a time constant for the standards select hunt period. An external RC sets the time constant. When a GS9005A Receiver is used, the open collector CARRIER DETECT output also connects to this pin in order to enable or disable the internal 2 bit binary counter which controls the hunting process. 12 V DD Power Supply. Most positive power supply connection. 13 V DD Power Supply. Most positive power supply connection. 14 SCE Input Sync Correction Enable. Active high CMOS input which enables sync correction by not resetting the GS9000C’s internal parallel timing on the first sync error. If the next incoming sync is in error, internal parallel timing will be reset. This is to guard against spurious HSYNC errors. When SCE is low, a valid sync will always reset the GS9000C’s parallel timing generator. Fig. 1 GS9000C Pin Outs, 28 Pin PLCC Package |
Аналогичный номер детали - GS9000CCTJ |
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Аналогичное описание - GS9000CCTJ |
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