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74LVC2G241DCUTG4 датащи(PDF) 9 Page - Texas Instruments |
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74LVC2G241DCUTG4 датащи(HTML) 9 Page - Texas Instruments |
9 / 24 page 1 2 6 1Y 1OE 1A 7 5 3 2Y 2OE 2A SN74LVC2G241 www.ti.com SCES210O – APRIL 1999 – REVISED DECEMBER 2015 8 Detailed Description 8.1 Overview The SN74LVC2G241 device is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LVC2G241 device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low and 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high and 2OE is low, the outputs are in the high-impedance state. The SN74LVC2G241 is also an effective redriver, with a maximum output current drive of 32 mA. 8.2 Functional Block Diagram Figure 3. Logic Diagram (Positive Logic) 8.3 Feature Description To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.4 Device Functional Modes Table 1 and Table 2 list the functional modes of the SN74LVC2G241. Table 1. Gate 1 Functional Table INPUTS OUTPUT 1Y 1OE 1A L H H L L L H X Z Table 2. Gate 2 Functional Table INPUTS OUTPUT 2Y 2OE 2A H H H H L L L X Z Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74LVC2G241 |
Аналогичный номер детали - 74LVC2G241DCUTG4 |
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Аналогичное описание - 74LVC2G241DCUTG4 |
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