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TPA3100D2RGZTG4 датащи(PDF) 2 Page - Texas Instruments |
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TPA3100D2RGZTG4 датащи(HTML) 2 Page - Texas Instruments |
2 / 41 page TPA3100D2 SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage AVCC, PVCC –0.3 V to 30 V SHUTDOWN, MUTE –0.3 V to VCC + 0.3 V VI Input voltage GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV, –0.3 V to VREG + 0.5 V SYNC Continuous total power dissipation See Thermal Information Table TA Operating free-air temperature range –40°C to 85°C TJ Operating junction temperature range(2) –40°C to 150°C Tstg Storage temperature range –65°C to 150°C RLoad Load Resistance 3.2 Ω Minimum Human body model (3) (all pins) ±2 kV Electrostatic discharge Machine model (4) (all pins) ±200 V Charged-device model (5) (all pins) ±500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The TPA3100D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad. (3) In accordance with JEDEC Standard 22, Test Method A114-B. (4) In accordance with JEDEC Standard 22, Test Method A115-A (5) In accordance with JEDEC Standard 22, Test Method C101-A THERMAL INFORMATION TPA3100D2 THERMAL METRIC(1) (2) UNITS RGZ (48 PINS) PHP (48 PINS) qJA Junction-to-ambient thermal resistance 25 28.7 qJCtop Junction-to-case (top) thermal resistance 16.5 19.2 qJB Junction-to-board thermal resistance 12.8 12.4 °C/W yJT Junction-to-top characterization parameter 0.2 0.2 yJB Junction-to-board characterization parameter 4.9 6.6 qJCbot Junction-to-case (bottom) thermal resistance 1.0 0.7 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VCC Supply voltage PVCC, AVCC 10 26 V SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, VIH High-level input voltage 2 V SYNC SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, VIL Low-level input voltage 0.8 V SYNC 2 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3100D2 |
Аналогичный номер детали - TPA3100D2RGZTG4 |
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Аналогичное описание - TPA3100D2RGZTG4 |
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