поискавой системы для электроныых деталей |
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TP11368 датащи(PDF) 9 Page - National Semiconductor (TI) |
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TP11368 датащи(HTML) 9 Page - National Semiconductor (TI) |
9 / 18 page Functional Description (Continued) CHANNEL NOP Each channel can be independently disabled. When EN is at logic low on the falling edge of CE, the ADPCM transcoder processing for that channel is disabled. The processor re- quires 4 CLK cycles for CE to maintain all channel variables. The data output ports are also placed in known states. After this the processor waits for the next interrupt. TSO outputs the following data after a channel NOP: TABLE 6. TSO at Channel NOP QSEL1 QSEL0 Mode TSO 0 0 32 kbps 0000 0 1 24 kbps 0000 1 0 16 kbps 0000 1 1 40 kbps 00000 The data pattern at TSO in Table 6 are shown with four ASCK clocks within the CE high pulse for the 32- , 24-, 16-kbps modes and five ASCK clocks within the CE high pulse for the 40 kbps mode. In the case where ASCK pulses are more than four or five, the given pattern recirculates with the MSB first. In the idle state, RSO outputs the following data (bit repre- sentation with the sign-bit on the left followed by the MSB, the sign-bit is the first bit after the rising edge of CE): TABLE 7. RSO at Channel NOP PCM1 Mode RSO 0 8-Bit µ-Law 11111111 1 8-Bit A-Law 11010101 9 www.national.com |
Аналогичный номер детали - TP11368 |
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Аналогичное описание - TP11368 |
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