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SI4703-B17 датащи(PDF) 8 Page - Silicon Laboratories |
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SI4703-B17 датащи(HTML) 8 Page - Silicon Laboratories |
8 / 42 page Si4703-B17 8 Confidential Rev. 1.0 Table 6. 2-Wire Control Interface Characteristics1 (VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fSCL 0— 400 kHz SCLK Low Time tLOW 1.3 — — µs SCLK High Time tHIGH 0.6 — — µs SCLK Input to SDIO Setup (START) tSU:STA 0.6 — — µs SCLK Input to SDIO Hold (START) t HD:STA 0.6 — — µs SDIO Input to SCLK Setup tSU:DAT 100 — — ns SDIO Input to SCLK Hold2,3 tHD:DAT 0— 900 ns SCLK input to SDIO Setup (STOP) t SU:STO 0.6 — — µs STOP to START Time tBUF 1.3 — — µs SDIO Output Fall Time tf:OUT 20 + 01.Cb —250 ns SDIO Input, SCLK Rise/Fall Time tf:IN tr:IN 20 + 01.Cb —300 ns SCLK, SDIO Capacitive Loading Cb —— 50 pF Input Filter Pulse Suppression tSP — — 50 ns Notes: 1. When VIO = 0 V, SCLK and SDIO are low impedance. 2. As a transmitter, the Si4703 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the 0 ns tHD:DAT specification. 3. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be violated so long as all other timing parameters are met. |
Аналогичный номер детали - SI4703-B17 |
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Аналогичное описание - SI4703-B17 |
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