UPD48288118AF1 datasheet(33/52 Pages) RENESAS

номер детали	UPD48288118AF1

подробное описание детали	288M-BIT Low Latency DRAM

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µµµµPD48288118AF1

R10DS0255EJ0101 Rev. 1.01

Page 33 of 51

Jan. 15, 2016

Figure 2-27. Mode Register Set Command in Multiplexed Address Mode

Notes 1. Bits A10–A17 must be set to all ‘0’. A18 is “Don’t Care”.

2. BL=8 is not available for configuration 1 and 4.

3. ±30% temperature variation.

4. Within 15%.

Remark

The address A0, A3, A4, A5, A8, and A9 must be set as follows in order to activate the mode register in

the multiplexed address mode.

Figure 2-28. Power-Up Sequence in Multiplexed Address Mode

Notes 1. Recommended all address pins held LOW during dummy MRS command.

2.

A10-A17 must be LOW.

3.

Address A5 must be set HIGH (muxed address mode setting when

µPD48288118AF1 is in normal mode of

operation).

4.

Address A5 must be set HIGH (muxed address mode setting when

µPD48288118AF1 is already in muxed

address mode).

Remark MRS : MRS command

RFp : REFRESH Bank p

AC : any command

VEXT

VDD

VDDQ

VREF

CK#

CK

COMMAND

200µs MIN.

tMRSC

tRC

MRS

RF0

RF1

RF7

AC

ADDRESS

VTT

A

MRS

Ax

Ay

tMRSC

1 cycle

MIN.

1 cycle

MIN.

NOP

Refresh all banks

15µs

A

Note 1, 2

Note 2, 3

Note 4

Don't care

A4

A5

A4

A3

A0

A8

A9

A3x

0

1

BL

4

A4x

0

1

8 Note 2

0

1

A9

A9y

0

1

A8

A4y A3y A0x

1

0

Configuration

1 Note 2 (default)

5

Reserved

1 Note 2

Not valid

2 (default)

PLL enabled

PLL Reset

Burst Length

PLL Reset

Address

Mux

Address Mux

PLL reset (default)

2

3

4

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Impedance

Matching

Impedance

Matching

A8x

0

1

Resistor

External

A5x

0

1

Nonmultiplexed

(default)

Address multiplexed

A9x

0

1

Enabled

Termination

Disabled (default)

On-Die

Termination

On-Die

Termination

Unused

Note 3

(default)

A17 ····· A10

Note 2

Note 4

Ay

Ax

A17 ····· A10

Reserved

Note 1

Аналогичный номер детали - UPD48288118AF1

производитель	номер детали	датащи	подробное описание детали
Renesas Technology Corp	UPD48288118AFF-E18-DW1	1Mb / 52P	288M-BIT Low Laten cy DRAM Separate I/O Oct 01, 2012
	UPD48288118AFF-E18-DW1-A	1Mb / 52P	288M-BIT Low Laten cy DRAM Separate I/O Oct 01, 2012
	UPD48288118AFF-E24-DW1	1Mb / 52P	288M-BIT Low Laten cy DRAM Separate I/O Oct 01, 2012
	UPD48288118AFF-E24-DW1-A	1Mb / 52P	288M-BIT Low Laten cy DRAM Separate I/O Oct 01, 2012
	UPD48288118AFF-E25-DW1	1Mb / 52P	288M-BIT Low Laten cy DRAM Separate I/O Oct 01, 2012

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Аналогичное описание - UPD48288118AF1

производитель	номер детали	датащи	подробное описание детали
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	UPD48288118-A	843Kb / 48P	288M-BIT Low Latency DRAM Separate I/O Feb 01, 2013
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	UPD48288109A	1Mb / 52P	288M-BIT Low Laten cy DRAM Separate I/O Oct 01, 2012
	UPD48576209	1Mb / 53P	576M-BIT Low Latency DRAM Common I/O Oct 01, 2012
	UPD48576109	1Mb / 52P	576M-BIT Low Latency DRAM Separate I/O Oct 01, 2012
Elpida Memory	EDR2518ABSE	1Mb / 79P	288M bits Direct Rambus DRAM

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