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UPD48576209F1 датащи(PDF) 48 Page - Renesas Technology Corp

номер детали UPD48576209F1
подробное описание детали  576M-BIT Low Latency DRAM
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD48576209F1 датащи(HTML) 48 Page - Renesas Technology Corp

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µµµµPD48576209F1, µµµµPD48576218F1, µµµµPD48576236F1
R10DS0256EJ0101 Rev. 1.01
Page 48 of 53
Jan. 15, 2016
JTAG Instructions
Many different instructions (28) are possible with the 8-bit instruction register. All used combinations are listed in
Table 3-8
, Instruction Codes. These six instructions are described in detail below. The remaining instructions are
reserved and should not be used.
The TAP controller used in this RAM is fully compliant to the 1149.1 convention. Instructions are loaded into the
TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this
state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction
once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
Table 3-8
Instructions
Instruction
Code [7:0]
Description
EXTEST
0000 0000
The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output pins are used to apply test vectors, while those
at input pins capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on
and the PRELOAD data is driven onto the output pins.
IDCODE
0010 0001
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the
controller is in capture-DR mode and places the ID register between the TDI and TDO
pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at
power up and any time the controller is placed in the test-logic-reset state.
SAMPLE / PRELOAD
0000 0101
SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the
SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP
controller into the capture-DR state loads the data in the RAMs input and DQ pins into
the boundary scan register. Because the RAM clock(s) are independent from the TAP
clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while
the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP
to sample metastable input will not harm the device, repeatable results cannot be
expected. RAM input signals must be stabilized for long enough to meet the TAPs input
data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the
boundary scan register. Moving the controller to shift-DR state then places the boundary
scan register between the TDI and TDO pins.
CLAMP
0000 0111
When the CLAMP instruction is loaded into the instruction register, the data driven by
the output balls are determined from the values held in the boundary scan register.
Selects the bypass register to be connected between TDI and TDO. Data driven by
output balls are determined from values held in the boundary scan register.
High-Z
0000 0011
The High-z instruction causes the boundary scan register to be connected between the
TDI and TDO. This places all RAMs outputs into a High-Z state.
Selects the bypass register to be connected between TDI and TDO. All outputs are
forced into high impedance state.
BYPASS
1111 1111
When the BYPASS instruction is loaded in the instruction register, the bypass register
is placed between TDI and TDO. This occurs when the TAP controller is moved to the
shift-DR state. This allows the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not
use these instructions.


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