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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT82R732 датащи(PDF) 34 Page - Holtek Semiconductor Inc |
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HT82R732 датащи(HTML) 34 Page - Holtek Semiconductor Inc |
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34 / 74 page  I/O Pin Structures The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, the I/O data register and I/O port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Pins PA0 to PA7, PB0 to PB7, PC1 to PC2 each has a wake-up function, selected via the PAWK, PBWK and PCWK registers respectively. When the device is in the HALT Mode, various methods are available to wake the device up. One of these is a high to low transition of any of these pins. Single or multiple pins on Port A, Port B or Port C can be setup to have this function. Rev. 1.00 34 October 31, 2013 HT82R732 e-Banking 8-Bit OTP MCU PA0~PA2 PA3/[PFD] PA4~PA7 PB0~PB3 PB4/PFD PB5/INT PB6/TC0 PB7/TC1 PC1~PC2 VDD M U X M U X PFDC Control Bit Data Bus Write Control Register Chip Reset Read Control Register WriteDataRegister Data Bit DQ CK S Q DQ CK S Q TC0 for PB6 only System Wake-up Read Data Register PB4 or PA3 PFD PAWK0~7/PBWK0~7/PCWK1~2 Pull-High Option TC1for PB7only Weak Pull-up INT for PB5 only Generic Input/Output Structure T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 W r i t e t o P o r t R e a d f r o m P o r t S y s t e m C l o c k P o r t D a t a Read Modify Write Timing |
Аналогичный номер детали - HT82R732 |
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Аналогичное описание - HT82R732 |
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