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KM681001B-20 датащи(PDF) 2 Page - Samsung semiconductor |
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KM681001B-20 датащи(HTML) 2 Page - Samsung semiconductor |
2 / 9 page KM681001B CMOS SRAM PRELIMINARY Rev 2.0 - 2 - February 1998 128K x 8 Bit High-Speed CMOS Static RAM GENERAL DESCRIPTION FEATURES • Fast Access Time 15, 20ns(Max.) • Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) Operating KM681001B - 15 : 125mA(Max.) KM681001B - 20 : 123mA(Max.) • Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Standard Pin Configuration KM681001BJ : 32-SOJ-400 KM681001BSJ : 32-SOJ-300 Clk Gen. I/O1 ~ I/O8 CS1 WE OE FUNCTIONAL BLOCK DIAGRAM Data Cont. Column Select CLK Gen. Pre-Charge Circuit Memory Array 512 Rows 256x8 Columns I/O Circuit PIN FUNCTION Pin Name Pin Function A0 - A16 Address Inputs WE Write Enable CS1, CS2 Chip Selects OE Output Enable I/O1 ~ I/O8 Data Inputs/Outputs VCC Power(+5.0V) VSS Ground N.C No Connection The KM681001B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681001B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung ′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681001B is packaged in a 400/300 mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) SOJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A16 CS2 WE A15 A14 A13 A12 OE A11 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 N.C A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 I/O2 I/O3 Vss CS2 A9 A10 A11 A12 A13 A14 A15 A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 |
Аналогичный номер детали - KM681001B-20 |
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Аналогичное описание - KM681001B-20 |
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