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GS8182D37BD-333I датащи(PDF) 11 Page - GSI Technology

номер детали GS8182D37BD-333I
подробное описание детали  JEDEC-standard pinout and package
Download  27 Pages
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8182D37BD-333I датащи(HTML) 11 Page - GSI Technology

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Thermal Impedance
Package
Test PCB
Substrate
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W)
θ JC (C°/W)
165 BGA
4-layer
19.1
15.9
14.9
7.2
2.3
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
GS8182D19/37BD-435/400/375/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 11/2011
11/27
© 2008, GSI Technology
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
DC Input Logic High
VIH (dc)
VREF + 0.1
VDD + 0.3
V
1, 4
DC Input Logic Low
VIL (dc)
–0.3
VREF – 0.1
V
1, 3
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing param-
eters.
3. VIL (Min)DC = –0.3 V, VIL(Min)AC = –1.5 V (pulse width ≤ 3 ns).
4. VIH (Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
AC Input Logic High
VIH (ac)
VREF + 200
mV
2, 3
AC Input Logic Low
VIL (ac)
VREF – 200
mV
2, 3
VREF Peak to Peak AC Voltage
VREF (ac)
5% VREF (DC)
mV
1
Notes:
1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.


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