поискавой системы для электроныых деталей |
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RT9116 датащи(PDF) 10 Page - Richtek Technology Corporation |
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RT9116 датащи(HTML) 10 Page - Richtek Technology Corporation |
10 / 11 page RT9116 10 DS9116-00 November 2016 www.richtek.com © Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 4. PCB Layout Guide Layout Considerations For the best performance of the RT9116, the below PCB layout guidelines must be strictly followed. Place the decoupling capacitors as close as possible to the AVCC, PVDDL, PVDDR and GND pins. For achieving a good quality, consider adding a small, good performance low ESR ceramic capacitor between 220pF and 1000pF and a larger mid-frequency capacitor between 0.1 μF and 1 μF to the PVDD pins of the chip. The traces of (LINP & LINN, RINP & RINN) and (OUTPL & OUTNL, OUTPR & OUTNR) should be kept equal width and length respectively. The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be larger for application. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. GND GND GND PVDD INPL INNL INNR INPR GVDD AVSS NC NC VOUTPL PVDDL VOUTNL BSTNL BSTNR VOUTNR PVDDR VOUTPR GND PVDD GND PVDD EN The decoupling capacitor (Cs) must be placed as close to the IC as possible The decoupling capacitor (Cs) must be placed as close to the IC as possible The decoupling capacitor (Cs) must be placed as close to the IC as possible CB CB CIN CIN CIN CIN The gate driver output decoupling capacitor (Cg) must be placed as close to the IC as possible Audio Input FB FB FB FB CB CB Cg GND PVSS (Thermal Pad) tied to GND |
Аналогичный номер детали - RT9116 |
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Аналогичное описание - RT9116 |
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