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GS82582D36E-375 датащи(PDF) 5 Page - GSI Technology

номер детали GS82582D36E-375
подробное описание детали  288Mb SigmaQuad-IITM Burst of 4 SRAM
Download  30 Pages
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS82582D36E-375 датащи(HTML) 5 Page - GSI Technology

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GS82582D18/36GE-400/375/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2016
5/30
© 2012, GSI Technology
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data
can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following
rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C,
and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read
port deselect cycle.
Read A
NOP
Read B
Write C
Read D
Write E
NOP
A
B
C
D
E
C
C+1
C+2
C+3
E
E+1
C
C+1
C+2
C+3
E
E+1
A
A+1
A+2
A+3
B
B+1
B+2
B+3
D
D+1
D+2
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ


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