Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample Time

BW0

BW1

D0–D8

D9–D17

Beat 1

0

1

Data In

Don’t Care

Beat 2

1

0

Don’t Care

Data In

Beat 3

0

0

Data In

Data In

Beat 4

1

0

Don’t Care

Data In

Resulting Write Operation

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Written

Unchanged

Unchanged

Written

Written

Written

Unchanged

Written

Beat 1

Beat 2

Beat 3

Beat 4

GS8662D08/09/18/36BD-400/350/333/300/250

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02d 8/2017

9/33

© 2011, GSI Technology

Output Register Control

SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output

Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the

output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K

and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to

function as a conventional pipelined read SRAM.