поискавой системы для электроныых деталей |
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SI5010-BM датащи(PDF) 11 Page - List of Unclassifed Manufacturers |
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SI5010-BM датащи(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 16 page Si5010 Preliminary Rev. 0.31 11 Differential Input Circuitry The Si5010 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 8. In applications where direct DC coupling is possible, the 0.1 µF capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6. Differential Output Circuitry The Si5010 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with AC coupling is shown in Figure 9. In applications in which direct DC coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6. Figure 8. Input Termination for DIN and REFCLK (AC Coupled) Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled) Differential Driver Si5010 0.1 µ F 0.1 µ F Zo = 50 Ω Zo = 50 Ω DIN+, REFC LK + DIN–, REFC LK – 2.5 k Ω 2.5 k Ω 10 k Ω 10 k Ω 102 Ω VDD GND DOUT–, CLKOUT– 50 Ω 50 Ω 0.1 µ F 0.1 µ F Zo = 50 Ω Zo = 50 Ω Si5010 VDD VDD 100 Ω 100 Ω VDD VDD DOUT+, CLKOUT+ |
Аналогичный номер детали - SI5010-BM |
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Аналогичное описание - SI5010-BM |
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