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SM561
Document #: 38-07021 Rev. *C
Page 6 of 8
SM560 Application Schematic
The schematic in Figure 3 demonstrates how SM561 is
configured in a typical application. This application uses a
65-MHz reference clock connected to pin 1. Because an
external reference clock is used, pin 8 (Xout) is left uncon-
nected.
Figure 3 also demonstrates how to properly use the Tri-level
Logic employed in the SM561. Note that resistors R2 and R4
create a voltage divider that places VDD/2 on pin 7 to satisfy
the voltage requirement for an “M” state.
With this configuration, the SM561 will produce an SSCG
clock that is at a center frequency of 65 MHz. Referring to
Table 1, range “0, M” at 65 MHz will generate a modulation
profile that has a 1.7% peak to peak spread.
Device
Cdiv
SM561
2332
(All Ranges)
Example:
Device
= SM561
Fin
= 65 MHz
Range
= S1 = 1, S0 = 0
Then;
Modulation Rate = Fmod = 65 MHz/2332 = 27.9 kHz.
Modulation Profile
Spectrum Analyzer
Figure 2. SSCG Clock, SM561, Fin = 65 MHz
VDD
VDD
65 MHz Reference Clock
VDD
R2
20 K
Application Load
R5
22
R4
20 K
SM561
Xin/CLK
1
VDD
2
GND
3
SSCLK
4
SSCC
5
S1
6
S0
7
Xout
8
C5
22 uF.
C6
0.1 uF
Figure 3. Application Schematic