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ST92F120JR1Q7 датащи(PDF) 11 Page - STMicroelectronics |
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ST92F120JR1Q7 датащи(HTML) 11 Page - STMicroelectronics |
11 / 324 page 11/324 ST92F120 - GENERAL DESCRIPTION 1.2.4.5 Power Supply and Ground As already said for the I/O pins, in order to guaran- tee ST9 compliancy with respect to Quality Assur- ance recommendations concerning ESD and Latchup, dedicated circuits are added to the differ- ent power supply and ground pins (digital and an- alog). These structures create preferred paths for the high current injected during discharges, avoid- ing damage to active logic and circuitry. It is impor- tant for the system designer to take this added cir- cuitry into account, which is not always transpar- ent with respect to the relative level of voltages ap- plied to the different power supply and ground pins. Figure 6 shows schematically the protection net implemented on ST9 devices, composed of di- odes and other special structures. The clamp structure between the VDD and VSS pins is designed to be active during very fast tran- sitions (typical of electrostatic discharges). Other paths are implemented through diodes: they limit the possibility of positively differentiating AVDD and VDD (i.e. AVDD > VDD); similar considerations are valid for AVSS and VSS due to the back-to- back diode structure implemented between the two pins. Anyway, it must be highlighted that, be- cause VSS and AVSS are connected to the sub- strate of the silicon die (even though in different ar- eas of the die itself), they represent the reference point from which all other voltages are measured, and it is recommended to never differentiate AVSS from VSS. Note: If more than one pair of pins for VSS and VDD is available on the device, they are connected internally and the protection net diagram remains the same as shown in Figure 6. Figure 6. Power Supply and Ground Configuration P P VDD VSS AVDD AVSS VTEST 9 |
Аналогичный номер детали - ST92F120JR1Q7 |
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Аналогичное описание - ST92F120JR1Q7 |
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