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MT9M114 датащи(PDF) 12 Page - ON Semiconductor

номер детали MT9M114
подробное описание детали  High?륞efinition (HD) System?륮n?륾?륝hip (SOC) Digital Image Sensor
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производитель  ONSEMI [ON Semiconductor]
домашняя страница  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MT9M114 датащи(HTML) 12 Page - ON Semiconductor

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12
IMAGE DATA OUTPUT INTERFACE
The user can select either the 8-bit parallel or serial MIPI
output to transmit the sensor image data to host system. Only
one of the output modes can be used at any time. The
MT9M114 has an output FIFO to retain a constant pixel
output clock independent from the data output rate
variations due to scaling factor.
Parallel Port
The MT9M114 image data is read out in a progressive
scan mode. Valid image data is surrounded by horizontal
blanking and vertical blanking. The amount of horizontal
blanking and vertical blanking are programmable.
MT9M114 output data is synchronized with the PIXCLK
output. When LV is HIGH, one pixel value is output on the
8-bit DOUT port every TWO PIXCLK periods as shown in
Figure 7. PIXCLK is continuously running, even during the
blanking period. (If the user wishes to have PIXCLK turned
off during blanking this is possible through a variable
setting) PIXCLK phase can be varied by 50 percent,
controlled using a register.
Figure 7. Pixel Data Timing Example
LINE_VALID
PIXCLK
DOUT[7:0]
P0 (9:2)
P0 (1:0)
P1 (9:2)
P2 (9:2)
P1 (1:0)
Pn−1(9:2)
Pn (9:2)
Pn (1:0)
Pn−1(1:0)
Valid Data
Blanking
Blanking
Figure 8. Row Timing, FV, and LV Signals
FRAME_VALID
LINE_VALID
Data Modes
P
1
A
2
Q
3
AQ
A
P
Notes:
1. P: Frame start and end blanking time.
2. A: Active data time.
3. Q: Horizontal blanking time.
Serial Port
This section describes how frames of pixel data are
represented on the high-speed MIPI serial interface. The
MIPI output transmitter implements a serial differential
sub-LVDS transmitter capable of up to 768 Mb/s. It supports
multiple formats, error checking, and custom short packets.
MT9M114 is designed to MIPI D-PHY version v1.0.
When the sensor is in the software standby system state,
the MIPI signals (CLK_P, CLK_N, DATA_P, DATA_N)
indicate ultra low-power state (ULPS) corresponding to
(nominal) 0 V levels being driven on CLK_P, CLK_N,
DATA_P, and DATA_N. This is equivalent to signaling code
LP−00. When the sensor enters the streaming system state,
the interface goes through the following transitions:
1. After the PLL has locked and the bias generator
for the MIPI drivers has stabilized, the MIPI
interface transitions from the ULPS state to the
ULPS-exit state (signaling code LP–10).
2. After a delay (TWAKEUP), the MIPI interface
transitions from the ULPS-exit state to the
TX-stop state (signaling code LP–11).
3. After a short period of time (the programmed
integration time plus a fixed overhead), frames of
pixel data start to be transmitted on the MIPI
interface. Each frame of pixel data is transmitted
as a number of high-speed packets. The transition
from the TX-stop state to the high-speed signaling
states occurs in accordance with the MIPI


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