MT9M131_17 datasheet(3/50 Pages) ONSEMI

номер детали	MT9M131

подробное описание детали	1/3?릋nch SOC 1.3Mp CMOS Digital Image Sensor

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производитель	ONSEMI [ON Semiconductor]

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MT9M131

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FUNCTIONAL OVERVIEW

The MT9M131 is a fully-automatic, single-chip camera,

requiring only a power supply, lens, and clock source for

basic operation. Output video is streamed through a parallel

8- or 10-bit DOUT port, shown in Figure 1.

Figure 1. Functional Block Diagram

Sensor Core

1316 (H) x 1048 (V) including black

1/3-inch optical format

Auto black compensation

Programmable analog gain

Programmable exposure

Dual 10-bit ADCs

Low-power preview mode

H/W context switch to/from preview

Bayer RGB output

Image Flow Processor

Camera Control

Auto exposure

Auto white balance

Flicker detect/avoid

Camera control:

snapshots, flash, video, clip

Image Flow Processor

Colorpipe

Lens shading correction

Color interpolation

Filtered resize and zoom

Defect correction

Color correction

Gamma correction

Color conversion + formatting

Output FIFO

SRAM

Line Buffers

Pixel Data

Control Bus

(Two-wire Serial I/F

Transactions)

Control Bus

(Two-wire Serial I/F

Transactions) + Sensor

Control (gains, shutter, etc.)

Control Bus

(Two-wire

Serial I/F

Trans.)

Image Data

DOUT[7:0]:

DOUT_LSB[1:0]

PIXCLK

FV

LV

STROBE

VAA_PIX

VAA/AGND

VDD/DGND

VDD_IO/DGNDIO

OE_BAR

STANDBY

EXTCLK

SDATA

SCLK

The output pixel clock is used to latch data, while FV and

LV signals indicate the active video. The MT9M131 internal

registers are configured using a two-wire serial interface.

The device can be put in low-power sleep mode by

asserting STANDBY and shutting down the clock. Output

pins can be tri-stated by de-asserting the OE_BAR. Both

tri-stating output pins and entry in standby mode also can be

achieved by two-wire serial interface register writes.

The MT9M131 accepts input clocks up to 54 MHz,

delivering up to 15 fps for SXGA resolution images, and up

to 30 fps for QSXGA (full field-of-view [FOV], sensor pixel

skipping) images. The device also supports a low-power

preview configuration that delivers SXGA images at 7.5 fps

and QSXGA images at 30 fps. The device can be

programmed to slow the frame rate in low light conditions

to achieve longer exposures and better image quality.

Internal Architecture

Internally, the MT9M131 consists of a sensor core and an

IFP. The IFP is divided in two sections: the colorpipe (CP),

and the camera controller (CC). The sensor core captures

raw Bayer-encoded images that are then input in the IFP. The

CP section of the IFP processes the incoming stream to

create interpolated, color-corrected output, and the CC

section controls the sensor core to maintain the desired

exposure and color balance, and to support snapshot modes.

The sensor core, CP, and CC registers are grouped in three

separate address spaces, as shown in Figure 2.

Аналогичный номер детали - MT9M131_17

производитель	номер детали	датащи	подробное описание детали
ON Semiconductor	MT9M131C12STC-DP	1Mb / 69P	CMOS Digital Image Sensor Rev. H 5/15 EN
	MT9M131C12STC-DR	1Mb / 69P	CMOS Digital Image Sensor Rev. H 5/15 EN
	MT9M131C12STC-TP	1Mb / 69P	CMOS Digital Image Sensor Rev. H 5/15 EN
	MT9M131C12STC-TR	1Mb / 69P	CMOS Digital Image Sensor Rev. H 5/15 EN

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