ADE7753

–4–

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

CS

SCLK

DIN

A4

A3 A2

A1 A0

DB7

Most Significant Byte

1

DB0

DB7

DB0

Least Significant Byte

00

Command Byte

CS

SCLK

DIN

A4 A3 A2

A1 A0

DB7

DOUT

DB0

DB0

DB7

Most Significant Byte

Least Significant Byte

000

Command Byte

Serial Write Timing

Serial Read Timing

Parameter

A,B Versions

Units

Test Conditions/Comments

Write timing

20

ns (min)

CS falling edge to first SCLK falling edge

150

ns (min)

SCLK logic high pulse width

150

ns (min)

SCLK logic low pulse width

10

ns (min)

Valid Data Set up time before falling edge of SCLK

5

ns (min)

Data Hold time after SCLK falling edge

T B D

ns (min)

Minimum time between the end of data byte transfers.

T B D

ns (min)

Minimum time between byte transfers during a serial write.

100

ns (min)

CS Hold time after SCLK falling edge.

Read timing

3.1

us (min)

Minimum time between read command (i.e. a write to Communication

Reigster) and data read.

T B D

ns (min)

Minimum time between data byte transfers during a multibyte read.

3

30

ns (min)

Data access time after SCLK rising edge following a write to the

Communications Register

4

100

ns (max)

Bus relinquish time after falling edge of SCLK.

10

ns (min)

4

100

ns (max)

Bus relinquish time after rising edge of

CS.

10

ns (min)

NOTES

and timed from a voltage level of 1.6V.

remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part

and is independent of the bus loading.

CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)