поискавой системы для электроныых деталей |
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TC554161AFTI-85 датащи(PDF) 8 Page - Toshiba Semiconductor |
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TC554161AFTI-85 датащи(HTML) 8 Page - Toshiba Semiconductor |
8 / 10 page TC554161AFTI-70,-85,-10,-70L,-85L,-10L 2001-08-17 8/10 Note: (1) R/W remains HIGH for the read cycle. (2) If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. DATA RETENTION CHARACTERISTICS (Ta ==== ----40° to 85°C) SYMBOL PARAMETER MIN TYP MAX UNIT VDH Data Retention Supply Voltage 2.0 ¾ 5.5 V VDH = 3.0 V ¾ ¾ 100 -70,-85,-10 VDH = 5.5 V ¾ ¾ 200 VDH = 3.0 V ¾ ¾ 50* IDDS2 Standby Current -70L,-85L,-10L VDH = 5.5 V ¾ ¾ 100 mA tCDR Chip Deselect to Data Retention Mode Time 0 ¾ ¾ ns tR Recovery Time 5 ¾ ¾ ms *: 5 mA (max) at Ta = -40° to 40°C CONTROLLED DATA RETENTION MODE Note: When CE is operating at the VIH level (2.4V), the standby current is given by IDDS1 during the transition of VDD from 4.5 to 2.6V. CE VDD 4.5 V GND VIH DATA RETENTION MODE tR (See Note) (See Note) tCDR VDD - 0.2 V CE |
Аналогичный номер детали - TC554161AFTI-85 |
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Аналогичное описание - TC554161AFTI-85 |
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