©2001 Fairchild Semiconductor Corporation

Rev. A, June 4, 2001

Thermal Resistance vs. Mounting Pad Area

thermal resistance of the heat dissipating path determines

an application. Therefore the application’s ambient

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

In using surface mount devices such as the SOP-8 package,

the environment in which it is applied will have a significant

influence on the part’s current and maximum power

and influenced by many factors:

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 23

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

maximum transient thermal impedance curve.

Electrical Specifications table. The points were chosen to

depict the compromise between the copper board area, the

thermal resistance and ultimately the power dissipation,

Thermal resistances corresponding to other copper areas

can be obtained from Figure 23 or by calculation using

times a cofficient added to a constant. The area, in square

inches is the top copper area including the gate and source

pads.

While Equation 2 describes the thermal resistance of a

single die, several of the new UltraFET™s are offered with

two die in the SOP-8 package. The dual die SOP-8 package

introduces an additional thermal component, thermal

coupling resistance,

function of the top copper mounting pad area.

The thermal coupling resistance vs. copper area is also

graphically depicted in Figure 23. It is important to note the

(

inches of copper:

die. The steady state junction temperature can be calculated

using Equation 4 for die 1and Equation 5 for die 2.

Example: To calculate the junction temperature of each die

when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0

Watts. The ambient temperature is 70°C and the package is

mounted to a top copper area of 0.1 square inches per die.

.

(EQ. 1)

P

DM

T

JM

T

A

–

()

-------------------------------

=

(EQ. 2)

RθJA

103.2

24.3

Area

()

ln

×

–

=

0

50

100

150

200

250

300

0.001

0.01

0.1

1

FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA

(EQ. 3)

Area

()

ln

×

–

=

(EQ. 4)

T

J1

P

1

++

=

(EQ. 5)

T

J2

P

2

++

=

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