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MC10EP51D датащи(PDF) 1 Page - ON Semiconductor |
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MC10EP51D датащи(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 3 1 Publication Order Number: MC10EP51/D MC10EP51, MC100EP51 3.3V / 5VECL D Flip-Flop with Reset and Differential Clock The MC10/100EP51 is a differential clock D flip–flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip–flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2. The 100 Series contains temperature compensation. • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: V CC = 3.0 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: V CC = 0 V with VEE = –3.0 V to –5.5 V • Open Input Default State • Safety Clamp on Inputs http://onsemi.com *For additional information, see Application Note AND8002/D L = Wafer Lot Y = Year W = Work Week H = MC10 K = MC100 A = Assembly Location SO–8 D SUFFIX CASE 751 MARKING DIAGRAMS* ALYW KEP51 ALYW HP51 TSSOP–8 DT SUFFIX CASE 948R ALYW HEP51 ALYW KP51 Device Package Shipping ORDERING INFORMATION MC10EP51D SO–8 98 Units/Rail MC10EP51DR2 SO–8 2500 Tape & Reel MC100EP51D SO–8 98 Units/Rail MC100EP51DR2 SO–8 2500 Tape & Reel MC10EP51DT TSSOP–8 100 Units/Rail MC10EP51DTR2 TSSOP–8 2500 Tape & Reel MC100EP51DT TSSOP–8 100 Units/Rail MC100EP51DTR2 TSSOP–8 2500 Tape & Reel 1 8 1 8 1 8 1 8 1 8 1 8 |
Аналогичный номер детали - MC10EP51D |
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Аналогичное описание - MC10EP51D |
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