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SLG46108 датащи(PDF) 40 Page - Dialog Semiconductor |
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SLG46108 датащи(HTML) 40 Page - Dialog Semiconductor |
40 / 70 page 000-0046108-108 Page 39 of 69 SLG46108 10.4 4-Bit LUT or 8-Bit Counter / Delay Macrocells There is one macrocell that can serve as either a 4-bit LUT or as a Counter / Delay. When used to implement LUT functions, the 4-bit LUT takes in four input signals from the connection matrix and produces a single output, which goes back into the connection matrix. When used to implement 8-Bit Counter / Delay function, two of the four input signals from the connection matrix go to the clock (CLK) and reset (DLY_IN/Reset_IN) inputs for the counter/delay, with the output going back to the connection matrix. This macrocell has an optional Finale State Machine (FSM) function. It has two additional matrix inputs for Up and Keep to support FSM functionality. The counter is counting down by deafault. Logic 1 on input Up reverses counting. Logic 1 on input Keep pauses counting. Figure 14. 4-bit LUT1 or CNT/DLY2/FSM0 CNT/DLY2/ FSM0 OUT CLK DLY_IN/Reset_IN 4-bit LUT0 OUT IN1 IN2 1-bit NVM IN3 IN0 To Connection Matrix Input <14> From Connection Matrix Output <27> reg <284:269> reg <285> From Connection Matrix Output <26> UP KEEP From Connection Matrix Output <28> From Connection Matrix Output <29> S0 S1 S0 S1 S0 S1 S0 S1 S0 S1 0: 4-bit LUT0 IN1 1: CNT/DLY2/FSM0 DLY_in/CNT_Reset 0: 4-bit LUT0 IN3 1: CNT/DLY2/FSM0 UP 0: 4-bit LUT0 IN0 1: DLY_in/CNT_Reset CLK 0: 4-bit LUT0 IN2 1: CNT/DLY2/FSM0 KEEP 0: 4-bit LUT0 OUT 1: CNT/DLY2/FSM0 OUT |
Аналогичный номер детали - SLG46108 |
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Аналогичное описание - SLG46108 |
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