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SLG46200 датащи(PDF) 28 Page - Dialog Semiconductor

номер детали SLG46200
подробное описание детали  GreenPAK Programmable Mixed Signal Array
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производитель  DIALOG [Dialog Semiconductor]
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SLG46200
11.2 ADC Operation Modes
The ADC has three operating modes:
Single-Ended ADC operation using IN+ from PIN 6, when ADC_sel (reg <350>) is “0”
Differential ADC operation using IN+ from PIN 6 and IN- from PIN 7, when ADC_sel (reg <350>) is “1”
Pseudo-Differential ADC operation using IN+ from PIN 6 and IN- from PIN 7, when ADC_sel (reg <350>) and ADC_gndoff_en
(reg <371>) bits are both set to “1”
11.3 ADC 3-bit Programmable Gain Amplifier
The front end of the ADC is a PGA with 3 bits for setting gain. The gain settings range from 0.5x to 16x. The PGA buffers the
ADC in all cases except with the singled ended gain is 0.5x. Single-ended PGA operation has gain settings of 0.5, 1, 2, 4, and
8x, while Differential operation has gain settings of 1, 2, 4, 8, and 16x. The PGA gain is set by the ADC_gain_control
(reg<353:351>). See ADC Register Settings Table.
For Pseudo-Differential mode, the PGA gain can only be 1x.
11.4 ADC 2-Channel Selection
When ADC_channel_sel (reg <339>) is set to “1”, the PGA of the ADC will sample either PIN 6 or PIN 7 on the IN+ input, where
the selection is controlled by PIN 2.
When PIN 2 is set to “0”, the ADC will sample PIN 7
When PIN 2 is set to “1”, the ADC will sample PIN 6
When ADC_channel_sel (reg <339>) is set to “0”, the PGA of the ADC will sample PIN 6 on the IN+ input
11.5 ADC Input Voltage Definition
The ADC’s input voltage (VIN_ADC) is calculated based on either the single-ended or differential operation modes the logic cell is
set to. In single-ended mode VIN_ADC is the sum of the positive input voltage and the gain of the PGA. While in differential mode
the VIN_ADC is the difference between the positive and negative input voltages times the gain of the PGA plus one half of the
reference voltage.
Figure 10. ADC 2-Channel Selection
Equation 1. ADC Input Voltage equation
1
0
PIN 6
reg <339>
CH SELECTOR (PIN 2)
Logic “1”
IN+
PIN 7
°¯
°
®
­

u

u



2
ref
gain
pga
in
in
gain
pga
in
adc
in
V
G
V
V
G
V
V
_
_
_
Single-ended mode
Differential mode


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