поискавой системы для электроныых деталей |
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SLG46400 датащи(PDF) 62 Page - Dialog Semiconductor |
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SLG46400 датащи(HTML) 62 Page - Dialog Semiconductor |
62 / 95 page 000-0046400-109 Page 56 of 89 SLG46400 17.5 Parallel to Serial Timing Diagram 17.6 S2P Notes Some functions of the S2P Converter share logic cells within the SLG46400, and as a result only one of these functions can be enabled at a time. The logic cells that are shared are: • S2P serial to parallel mode or S2P parallel to serial out • S2P parallel to serial mode or ADC serial output data on PIN 6 • S2P parallel to serial mode or DLY3 logic cell 17.7 S2P Register Settings Figure 33. Parallel to Serial Timing Diagram Table 26. S2P Register Settings Signal Function Register Bit Address Register Definition S2P Output Enable (PIN6) <712:711> 00: Disable 01: Disable 10: Enable 11: Disable S2P Mode Select <804> 0: Serial Input (from PIN 6)/Parallel Output 1: Parallel Input (from CNT1)/Serial Output S2P Clock Enable <805> 0: Disable 1: Enable SCLK MISO MSB 4 63 51 LSB 2 nCSB CAPTURE |
Аналогичный номер детали - SLG46400 |
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Аналогичное описание - SLG46400 |
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