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ML145488-4P датащи(PDF) 7 Page - LANSDALE Semiconductor Inc. |
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ML145488-4P датащи(HTML) 7 Page - LANSDALE Semiconductor Inc. |
7 / 12 page www.lansdale.com Page 7 of 12 Issue A LANSDALE Semiconductor, Inc. ML145488 It is impossible to precisely predict what the DDLC bus oc- cupancy will be, but worst case with both channels operating full–duplex at 64 kbps (aggregate rate of 256 kbps) in a16–bit 68000 system with a 12 MHz MCLK, approximately 0.66% of the host bus bandwidth is consumed by the DDLC. Bus occupan- cy increases linearly with data rate. At very high data rates, laten- cy from the bus request to the bus grant and interrupt service latency become the limiting factors. It must also be kept in mind that the DDLC can generate interrupts quickly, especially with a large number of small data packets at a high clock rate. Buffer Descriptors As previously stated, the DDLC has four DMA channels. Pointer registers and counters are required so that the DMA con- troller knows where to place or fetch data in memory. Transmit Buffer Descriptors When the host has a frame of data to transmit, it informs the DMA controller where the data resides in memory. A16–bit regis- ter, the Transmit Base Address register, points to the first word of the transmitted frame and provides a 64 kbyte address range. The host programs the address of the first word to be transmitted into this register. The length of the data frame must also be given to the DMA controller, so a 12–bit Transmit Frame Length register is used to indicate the length of the frame in bytes. Frames of up to 4096 bytes in length may be transmitted. Back to back frames can be transmitted by updating the transmit buffers when the Transmit DMA Complete interrupt is generated. NOTE Once a transmit buffer descriptor has been prepared, it must not be disturbed until the transmit DMA complete or transmit frame complete interrupts are generated. Receive Buffer Descriptors The receive buffer descriptors have a 16–Bit Receive Buffer Base Address register, a 12–Bit Buffer Length register, and a 12–Bit Frame Length register. The 16–Bit Base Address register provides 64 kbyte address range and contains the address of the first word of the data buffer to accept a data frame. The 12–Bit Frame Length register indicates the length of the memory buffer in bytes. Buffers of up to 4096 bytes may be built. The DMA con- troller never places data outside of the boundaries set–up by these two registers. The Frame Length register indicates the number of bytes (including the CRC) received. Each channel has a pair of buffer descriptors. These may be used alternately so that while one buffer is filling, another buffer is ready–in–waiting. If back–to–back data frames are received, after the first buffer has been closed the second is immediately ready for the next frame. There must be at least one buffer ready to accept data when the Rx Enable bit is set. Figure 6 describes the activity of the receiver with four buffers in memory. If a packet is being received and no buffers are ready, the receive FIFO will overrun, the Receiver Enable bit is reset, and an interrupt is queued indicating the overrun. If both descriptors are ready, then Buffer A is filled first. If a received frame is larger than a buffer, the Buffer (A or B) Overrun Interrupt is queued, but the receiver continues to receive and the DMA controller places the data in the alternate buffer (if it is available). If an alternate buffer is not ready, the Rx FIFO Overrun Interrupt is generated and the receiver is reset. Once a data frame has been completely received, the number of bytes received is indicated in the Frame Length register. The number in this register is valid only when the receive DMA Complete bit (Buffer A or Buffer B) in the Receive Status register is set to ‘1’. NOTE As with the transmitter, once a receive buffer des- criptor has been prepared, it must not be disturbed until the closing flag has been found and DMA activ- ity on the buffer has stopped. Address Expansion The DDLC provides signals for expansion of the 64 kbyte address space. The OWN pins are activated with timing identical to the address pins to enable external address expansion circuitry onto the address bus. Using the OWN pins with the R/W pin, the transmit and receive buffers may all be on separate 64 kbyte pages in memory. Transmit Channel Operation Figure 5 is a simplified state diagram of the DMA controller’s operation when a transmit channel requests service. Four interrupts are produced by the transmitter DMA channel. Transmit DMA Complete indicates that the last byte of data has been transferred from the buffer into the transmit FIFO. FIFO Underrun indicates the DMA requests were not serviced and the FIFO underran. Bus Error is generated when the BERR pin is activated during a DMA cycle. Address Error is generated when either IACK or CS are activated during a DMA cycle. Receive Channel Operation Figure 7 is a simplified state diagram for operation of the DMA controller when a receive channel requests service. MICROPROCESSOR INTERFACE The microprocessor block interfaces the internal 16–bit bus to the host 8– or 16–bit bus. The block also performs all timing con- version and buffering. This block has three modes of operation described in this section: system slave, system master, and inter- rupt generator. System Slave Mode When the DDLC is in this mode, it appears as fast memory to the host processor. The host can read from or write to the registers in the DDLC. This mode is entered when the CS pin is activated. Internal address decoding circuitry is selected and the desired reg- ister is connected to the internal bus for access by the host. |
Аналогичный номер детали - ML145488-4P |
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Аналогичное описание - ML145488-4P |
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