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MB39C603 датащи(PDF) 13 Page - Cypress Semiconductor

номер детали MB39C603
подробное описание детали  Phase Dimmable PSR LED Driver IC for LED Lighting
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB39C603 датащи(HTML) 13 Page - Cypress Semiconductor

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Document Number: 002-08450 Rev. *B
Page 13 of 30
MB39C603
8.5
Power-On Sequence
When the AC line voltage is supplied, VBULK is powered from the AC line through a diode bridge, and the VDD pin is charged from
VBULK through an external source-follower BiasMOS.(Figure 8-4 red path)
When the VDD pin is charged up and the voltage on the VDD pin (VVDD) rises above the UVLO threshold voltage, an internal Bias
circuit starts operating, and MB39C603 starts the conduction angle detection (refer to 8.3). After the UVLO is released, this device
enables switching and is operating in a forced switching mode (TON = 1.5 µs, TOFF = 78 µs to 320 µs). When the voltage on the TZE
pin reaches the Zero energy threshold voltage (VTZETH = 0.7V), MB39C603 enters normal operation mode. After the switching
begins, the VDD pin is also charged from Auxiliary Winding through an external diode (DBIAS).(Figure 8-4 blue path)
During non-conduction period VVDD is not supplied from VBULK or Auxiliary Winding. It is necessary to set an appropriate capacitor
of the VDD pin in order to keep VVDD above the UVLO threshold voltage in this period. An external diode (D1) between BiasMOS
and the VDD pin is used to prevent discharge from the VDD pin to VBULK at zero cross points of the AC line voltage.
Figure 8-4 VDD Supply Path at Power-On
UVLO
VDD
DRV
CS
GND
Internal Bias
Generator
Driver
VBULK
Rst
Zbias
Bias
MOS
PWM
Control
Logic
To TZE
DBIAS
D1
13
11
12
2
Phase
Dimmer
Figure 8-5 Power-On Waveform
VBULK
DRV
VDD
VLED
TZE
VTZETH = 0.7V
Force switching (ton=1.5us / toff=78us~320us)
Switching start
UVLO Vth = 10.2V
Normal switching


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