поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

CY7C1460KV33 датащи(PDF) 1 Page - Cypress Semiconductor

номер детали CY7C1460KV33
подробное описание детали  36-Mbit (1M36/2M18) Pipelined SRAM with NoBL??Architecture (With ECC)
Download  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1460KV33 датащи(HTML) 1 Page - Cypress Semiconductor

  CY7C1460KV33 Datasheet HTML 1Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 2Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 3Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 4Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 5Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 6Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 7Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 8Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 9Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 31 page
background image
36-Mbit (1M × 36/2M × 18) Pipelined SRAM
with NoBL™ Architecture (With ECC)
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-66680 Rev. *L
Revised February 8, 2018
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
Pin-compatible and functionally equivalent to Zero Bus
Turnaround (ZBT™)
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250, 200, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully-registered (inputs and outputs) for pipelined operation
Byte write capability
3.3-V power supply
3.3-V/2.5-V I/O power supply
Fast clock-to-output time
2.5 ns (for 250-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1460KV33,
CY7C1460KVE33,
CY7C1462KVE33
available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 165-ball FBGA packages
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability—linear or interleaved burst order
“ZZ” sleep mode option
On-chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
Functional Description
The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are
3.3 V, 1M × 36, and 2M × 18 synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations
with
no
wait
states.
The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle.
This feature dramatically improves the throughput of data in
systems that require frequent write and read transitions. The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd
for
CY7C1460KV33/CY7C1460KVE33
and
BWa–BWb for CY7C1462KVE33) and a write enable (WE) input.
All writes are conducted with on-chip synchronous self-timed
write circuitry.
Three synchronous chip enables (CE1, CE2, and CE3) and an
asynchronous output enable (OE) enable easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum access time
2.5
3.2
3.4
ns
Maximum operating current
× 18
220
190
170
mA
× 36
240
210
190


Аналогичный номер детали - CY7C1460KV33

производительномер деталидатащиподробное описание детали
logo
Cypress Semiconductor
CY7C1460KV25 CYPRESS-CY7C1460KV25 Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV25-167AXC CYPRESS-CY7C1460KV25-167AXC Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV25-167BZC CYPRESS-CY7C1460KV25-167BZC Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV25-167BZXI CYPRESS-CY7C1460KV25-167BZXI Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV25-200BZI CYPRESS-CY7C1460KV25-200BZI Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
More results

Аналогичное описание - CY7C1460KV33

производительномер деталидатащиподробное описание детали
logo
Cypress Semiconductor
CY7C1460KV25 CYPRESS-CY7C1460KV25 Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460SV25 CYPRESS-CY7C1460SV25 Datasheet
429Kb / 31P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture
CY7C1370KV33 CYPRESS-CY7C1370KV33 Datasheet
999Kb / 32P
   18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1440KV33 CYPRESS-CY7C1440KV33 Datasheet
3Mb / 33P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined Sync SRAM (With ECC)
CY7C1461KV33 CYPRESS-CY7C1461KV33 Datasheet
2Mb / 23P
   36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM with NoBL??Architecture
CY7C1370KV25 CYPRESS-CY7C1370KV25 Datasheet
2Mb / 30P
   18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture
CY7C1370B CYPRESS-CY7C1370B Datasheet
759Kb / 27P
   512K 횞 36/1M 횞 18 Pipelined SRAM with NoBL Architecture
CY7C1371KV33 CYPRESS-CY7C1371KV33 Datasheet
682Kb / 24P
   18-Mbit (512K 횞 36/1M 횞 18) Flow-Through SRAM with NoBL??Architecture (With ECC)
CY7C1441KV33 CYPRESS-CY7C1441KV33 Datasheet
1Mb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM (With ECC)
CY7C1460BV25 CYPRESS-CY7C1460BV25 Datasheet
721Kb / 30P
   36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


датащи скачать

Go To PDF Page


ссылки URL




Конфиденциальность
ALLDATASHEETRU.COM
Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com