11

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FSBB20CH60 Rev. C

Note:

1. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s

printed circuit board. The SPM input signal section integrates 3.3k

Ω(typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the sig-

nal voltage drop at input terminal.

2. The logic input is compatible with standard CMOS or LSTTL outputs.

Figure 9. Recommended CPU I/O Interface Circuit

Note:

high-side.

Figure 10. Recommended Bootstrap Operation Circuit and Parameters

CPU

COM

5V-Line

1nF

Ω

4.7k

,,

IN

(UL)

IN

(VL)

IN

(W L)

,,

IN

(UH)

IN

(VH)

IN

(W H)

V

FO

Ω

100

1nF

SPM

R

C

15V-Line

22uF

0.1uF

1000uF

1uF

One-Leg Diagram of SPM

Vcc

IN

COM

VB

HO

VS

Vcc

IN

COM

OUT

Inverter

Output

P

N

These Values depend on PW M Control Algorithm

D

BS

R

BS

R

E(H)

V

SL