TLF6588

August 1989

DM7556DM8556 TRI-STATE

Programmable

Binary Counters

General Description

These circuits are synchronous edge-sensitive fully-pro-

grammable 4-bit counters The counters feature both con-

ventional totem-pole and TRI-STATE outputs such that

when the outputs are in the high impedance mode they can

be used to enter data from the bus lines In addition the

clear input operates completely independent of all other in-

puts During the programming operation data is loaded into

the flip-flops on the positive-going edge of the clock pulse

To facilitate cascading of these counters the MAX COUNT

output can be tied directly into the count enable input of the

next counter

Features

Y

Typical clock frequency 35 MHz

Y

TRI-STATE outputs

Y

Fully independent clear

Y

Synchronous loading

Y

Cascading circuitry provided internally

Connection Diagram

Dual-In-Line Package

TLF6588 – 1

Order Number DM7556J or DM8556N

See NS Package Number J16A or N16A

Function Table

Control Inputs

IO Ports

Active Outputs

LOAD

CE

CLK

OD

Reset

HX

X

L

H

L

L

L

L

L

L

L

L

HX

X

H

H

Z

Z

Z

ZL

L

L

L

HX

L

L

L

HX

L

H

L

Z

Z

Z

Z

LH

u

LL

a

b

c

d

A

B

C

D

HL

u

L

L

COUNT

COUNT

HL

u

H

L

Z

Z

Z

Z

COUNT

The IO pins are used as inputs when they are TRI-STATED and the LOAD input is Low They are outputs and active

when LOAD input is High and OD is Low

were established

TRI-STATE

is a registered trademark of the National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A