DAC5674

SLWS148 − SEPTEMBER 2003

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5

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,

IOUTFS = 20 mA, differential transformer coupled output, 50-

Ω doubly terminated load (unless otherwise noted)

DIGITAL SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CMOS INTERFACE

VIH

High-level input voltage for SLEEP and EXTLO

0.7xAVDD

V

VIL

Low-level input voltage for SLEEP and EXTLO

0

0.3xAVDD

V

VIH

High-level input voltage other digital inputs

0.7xIOVDD

V

VIL

Low-level input voltage other digital inputs

0

0.3xIOVDD

V

IIH

High-level input current

10

30

µA

IIL

Low-level input current

−1

10

µA

Input capacitance

1

5

pF

TIMING INTERNAL CLOCK MODE

tSU

Input setup time

0.6

ns

tH

Input hold time

0.6

ns

tLPH

Input latch pulse high time

2

ns

tlat_2x

Data in to DAC out latency − 2X interpolation

26

clk

tlat_4x

Data in to DAC out latency − 4X interpolation

35

clk

TIMING − EXTERNAL CLOCK MODE

tsu

Input setup time

5

ns

th

Input hold time

−1.75

ns

tlph

Input latch pulse high time

2

ns

td_clk

Clock delay time

3.6

ns

tlat_2x

Data in to DAC out latency − 2X interpolation

26

clk

tlat_4x

Data in to DAC out latency − 4X interpolation

35

clk

PLL

Input data rate supported

5

200

MSPS

Phase noise

At 600-kHz offset

−124

dBc/Hz

Phase noise

At 6-MHz offset

−134

dBc/Hz

DIGITAL FILTER SPECIFICATIONS

fDATA

Input data rate

200

MSPS

FIR1 and FIR2 DIGITAL FILTER CHARACTERISTICS

0.005 db

0.407

Passband width

0.01 dB

0.41

fOUT/

Passband width

0.1 dB

0.427

fOUT/

fDATA

3 dB

0.481

fDATA