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HV7161SPA2 датащи(PDF) 56 Page - List of Unclassifed Manufacturers |
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HV7161SPA2 датащи(HTML) 56 Page - List of Unclassifed Manufacturers |
56 / 72 page HV7161SPA2 CMOS Image Sensor Confidential With Image Signal Processing This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 56 - 2005 MagnaChip Semiconductor Ltd. 7 6 5 4 3 2 1 0 Reserved PLL Feedback Divisor High 0 0 0 0 0 0 0 0 PLL Feedback Divisor Low [PFDDIVL : a5h : 02h] 7 6 5 4 3 2 1 0 PLL Feedback Divisor Low 0 0 0 0 0 0 1 0 The operation frequency of PLL is related to the proportion of Reference(PREFDIV) to Feedback(PFDDIV) Divisor. F(ck) is actually determined by the following equation. ) ( ) ( ) ( ) ( Divisor eference R Divisor Feedback ref F ck F ∗ = F(ck) : frequency of output F(ref) : frequency of PLL input Feedback Divisor : PFDDIV[13:0] + 2 Reference Divisor : PREFDIV[7:0] + 1 Data Output Timing and Interface Y [ 7 : 0 ] V C L K H S Y N C X Y 0 Y 1 Y 2 4 n s ~ 5 n s 1 4 n s ~ 1 5 n s M C L K As specified is the above data output timing diagram, the timing margin between video clock pin(VCLK) and data pins(Y[7:0]) is about 4n~5ns. This margin may be sufficient or not according to how much video clock and data pins are delayed internally in the backend chip, respectively. To safely latch the data output in the backend chip, it is recommended that data be latched at negative edge of VCLK. The above timing margin diagram represents 16bit output interface, but is also valid for 8bit output interface.. |
Аналогичный номер детали - HV7161SPA2 |
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Аналогичное описание - HV7161SPA2 |
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