поискавой системы для электроныых деталей |
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MC740-430E датащи(PDF) 11 Page - List of Unclassifed Manufacturers |
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MC740-430E датащи(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 15 page - 11 - NEL MC740-430E Step 1 CLK10 output Insert a phase shifter between CLK10 output terminal and the PPG. Phase shift range of the phase shifter should be 100 pspp. Observe the 20 Gb/s monitor outputs by using the oscilloscope. If the CLK10 delay is not optimum, the monitor outputs will be similar to Fig. 6(a). Adjust the CLK10 delay until the monitor output becomes clear (see Fig. 6(b)). When the 20G monitor outputs become clear, the 40G monitor output automatically becomes clear. (a) with an unsuitable delay (b) after delay adjustment Fig. 6. 20G and 40G monitor output waveforms. Informally, similar adjustment could be done by shifting the delay of CLK10 input (clock delay time from PPG). The output timing from the latching stage, or input data timing for the 4:1 MUX, can be controlled by CLK10 input as shown in Fig. 7. However, this method cannot be applicable for all situations because the clock phase margin of the latching stage is smaller than 360 degree. Latching stage 4:1 MUX internal clock 4 4 latched data DATA 3, 2, 1, 0 CLK10 input Fig. 7. Delay adjustment by CLK10 input. 20Gb/s odd 500 mV/div 40Gb/s 150 mV/div 20Gb/s even 500 mV/div 20Gb/s odd 500 mV/div 40Gb/s 150 mV/div 20Gb/s even 500 mV/div 20 psV/div 20 psV/div |
Аналогичный номер детали - MC740-430E |
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Аналогичное описание - MC740-430E |
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