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ATMEGA1280 датащи(PDF) 31 Page - ATMEL Corporation

номер детали ATMEGA1280
подробное описание детали  8- BIT Microcontroller with 256K Bytes In-System Programmable Flash
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производитель  ATMEL [ATMEL Corporation]
домашняя страница  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATMEGA1280 датащи(HTML) 31 Page - ATMEL Corporation

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ATmega640/1280/1281/2560/2561
2549A–AVR–03/05
Timing
External Memory devices have different timing requirements. To meet these require-
ments, the XMEM interface provides four different wait-states as shown in Table 5. It is
important to consider the timing specification of the External Memory device before
selecting the wait-state. The most important parameters are the access time for the
external memory compared to the set-up requirement. The access time for the External
Memory is defined to be the time from receiving the chip select/address until the data of
this address actually is driven on the bus. The access time cannot exceed the time from
the ALE pulse must be asserted low until data is stable during a read sequence (See
t
LLRL+ tRLRH - tDVRH in Tables 169 through Tables 176 on pages 376 - 378). The different
wait-states are set up in software. As an additional feature, it is possible to divide the
external memory space in two sectors with individual wait-state settings. This makes it
possible to connect two different memory devices with different timing requirements to
the same XMEM interface. For XMEM interface timing details, please refer to Table 169
to Table 176 and Figure 161 to Figure 164 in the “External Data Memory Timing” on
page 376.
Note that the XMEM interface is asynchronous and that the waveforms in the following
figures are related to the internal system clock. The skew between the internal and
external clock (XTAL1) is not guarantied (varies between devices temperature, and sup-
ply voltage). Consequently, the XMEM interface is not suited for synchronous operation.
Figure 16. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the
next instruction accesses the RAM (internal or external).
ALE
T1
T2
T3
WR
T4
A15:8
Address
Prev. addr.
DA7:0
Address
Data
Prev. data
XX
RD
DA7:0 (XMBK = 0)
Data
Prev. data
Address
Data
Prev. data
Address
DA7:0 (XMBK = 1)
System Clock (CLKCPU)
XXXXX
XXXXXXXX


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