CDC392

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

SCAS335A – DECEMBER 1992 – REVISED NOVEMBER 1995

1

POST OFFICE BOX 655303

and Clock-Generation Applications

CMOS-Compatible Outputs

Outputs

Complementary Outputs

Switching Noise

Significantly Reduces Power Dissipation

description

The CDC392 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew

for clock distribution. Through the use of the polarity-control (T/C) inputs, various combinations of true and

complementary outputs can be obtained. The output-enable (OE) input is provided to disable the outputs to a

high-impedance state.

The CDC392 is characterized for operation from – 40

°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUT

OE

T/C

A

Y

H

X

X

Z

L

LL

L

L

LH

H

L

HL

H

L

H

H

L

Copyright

© 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC-

ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

1Y2

1Y3

GND

2Y1

2Y2

GND

3Y1

1Y1

1T/C

2T/C

A

3T/C

OE