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DM5476 датащи(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали DM5476
подробное описание детали  Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
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DM5476 датащи(HTML) 1 Page - National Semiconductor (TI)

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TLF6528
June 1989
5476DM5476DM7476
Dual Master-Slave J-K Flip-Flops with Clear
Preset and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs The J and
K data is processed by the flip-flop after a complete clock
pulse While the clock is low the slave is isolated from the
master On the positive transition of the clock the data from
the J and K inputs is transferred to the master While the
clock is high the J and K inputs are disabled On the nega-
tive transition of the clock the data from the master is trans-
ferred to the slave The logic state of J and K inputs must
not be allowed to change while the clock is high The data is
transfered to the outputs on the falling edge of the clock
pulse A low logic level on the preset or clear inputs will set
or reset the outputs regardless of the logic levels of the
other inputs
Features
Y
Alternate MilitaryAerospace device (5476) is available
Contact a National Semiconductor Sales OfficeDistrib-
utor for specifications
Connection Diagram
Dual-In-Line Package
TLF6528 – 1
Order Number 5476DMQB 5476FMQB
DM5476J DM5476W or DM7476N
See NS Package Number J16A N16E or W16A
Function Table
Inputs
Outputs
PR
CLR
CLK
J
K
Q
Q
LH
X
X
X
H
L
HL
X
X
X
L
H
LL
X
X
X
H
H
HH
LL
Q0
Q0
HH
HL
H
L
HH
LH
L
H
HH
H
H
Toggle
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
e
Positive pulse data The J and K inputs must be held constant while
the clock is high Data is transfered to the outputs on the falling edge of the
clock pulse
e
This configuration is nonstable that is it will not persist when the preset
andor clear inputs return to their inactive (high) level
Q0 e The output logic level before the indicated input conditions were es-
tablished
Toggle e Each output changes to the complement of its previous level on
each complete active high level clock pulse
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A


Аналогичный номер детали - DM5476

производительномер деталидатащиподробное описание детали
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Texas Instruments
DM5474 TI1-DM5474 Datasheet
358Kb / 8P
[Old version datasheet]   Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
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DM5475 NSC-DM5475 Datasheet
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Аналогичное описание - DM5476

производительномер деталидатащиподробное описание детали
logo
Fairchild Semiconductor
DM7476 FAIRCHILD-DM7476_01 Datasheet
47Kb / 4P
   Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM7476 FAIRCHILD-DM7476 Datasheet
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Texas Instruments
SN5472 TI-SN5472 Datasheet
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National Semiconductor ...
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Fairchild Semiconductor
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