NV25M01

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6

Write Operations

The NV25M01 device powers up into a write disable

state. The Write Enable Latch (WEL) bit must be set before

attempting to write to memory or to the status register. In

addition, the address of the memory location(s) to be written

must be outside the protected area, as defined by the BP0 and

BP1 status register bits.

Write Enable and Write Disable

The internal Write Enable Latch and the correspon–ding

Status Register WEL bit are set by sending the WREN

instruction to the NV25M01. Care must be taken to take the

CS input high after the WREN instruction, as otherwise the

Write Enable Latch will not be properly set. WREN timing

is illustrated in Figure 3. The WREN instruction must be

sent prior any WRITE or WRSR instruction.

The internal Write Enable Latch is reset by sending the

WRDI instruction as shown in Figure 4. Disabling write

operations by resetting the WEL bit, will protect the device

against inadvertent writes.

Figure 3. WREN Timing

SCK

SI

SO

00

0

0

0

11

0

HIGH IMPEDANCE

Note: Dashed Line = mode (1, 1)

CS

Figure 4. WRDI Timing

SCK

SI

SO

00

0

0

0

10

0

HIGH IMPEDANCE

Note: Dashed Line = mode (1, 1)

CS