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AD8139 датащи(PDF) 7 Page - Analog Devices

номер детали AD8139
подробное описание детали  Low Noise Rail-to-Rail Differential ADC Driver
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD8139 датащи(HTML) 7 Page - Analog Devices

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AD8139
Rev. A | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
12 V
VOCM
±VS
Power Dissipation
See Figure 3
Input Common-Mode Voltage
±VS
Storage Temperature
–65°C to +125°C
Operating Temperature Range
–40°C to +125°C
Lead Temperature Range
(Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only; functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, i.e., θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
Unit
SOIC-8 with EP/4-Layer
70
°C/W
LFCSP/4-Layer
70
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8139 package is
limited by the associated rise in junction temperature (TJ) on the
die. At approximately 150°C, which is the glass transition tem-
perature, the plastic will change its properties. Even temporarily
exceeding this temperature limit may change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8139. Exceeding a junction temperature of
175°C for an extended period of time can result in changes in the
silicon devices potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θJA. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground, and
power planes will reduce the θJA.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
(EP) SOIC-8 (θJA = 70°C/W) package and LFCSP (θJA =
70°C/W) on a JEDEC standard 4-layer board. θJA values are
approximations.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (
°C)
SOIC
AND LFCSP
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.


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