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KFM1G16Q2M-DED6 датащи(PDF) 3 Page - Samsung semiconductor |
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KFM1G16Q2M-DED6 датащи(HTML) 3 Page - Samsung semiconductor |
3 / 124 page MuxOneNAND1G(KFM1G16Q2M-DEB5) FLASH MEMORY 3 MuxOneNAND2G(KFN2G16Q2M-DEB5) Document Title MuxOneNAND Revision History Revision No. 0.0 0.1 0.2 0.3 Remark Draft Advance Preliminary Preliminary Draft Date Dec. 3, 2003 May 19, 2004 Nov. 4, 2004 Jan. 10, 2005 History Initial issue. 1. Corrected the errata 2. Added Data Protection Scheme during Power-down 3. ECC description is revised. 4. Added Read while Load and Write While Program diagram. 5. Revised and added OTP description. 6. Added Write Protection description 7. Added Multi Block Erase operation notes 8. Added NAND Array Memory Map 9. RDY Conf bit in System Configuration Register is added. 10. Controller Status Register is revised. 11. Added DC/AC parameters 12. Revised OTP area assignment 13. Added the Addressing for program operation 14. Added INT guidance 15. Added Reset descriptions. 16. Revised Status Flag 1. Updated all description with a new format 1. Corrected the errata 2. Revised typical value of ISB from 50uA to 10uA 3. Revised maximum value of ISB from 100uA to 50uA 4. Revised erase current as TBD 5. Revised maximum value of tCE, tAA and tACC from 70ns to 76ns 6. Revised Vcc-IO description 7. Revised Spare Area description 8. Added Version ID Register information 9. Added extra information on Controller Status Register 10. Added commands related to Interrupt Status Register bits 11. Revised Write Protection Status on Chapter 3.4.3 12. Revised Copy-Back Program Operation description 13. Added Copy-Back Program Operation with Random Data Input 14. Added extra information on Multi-Block Erase Operation 15. Disabled FBA restriction in OTP operation 16. Revised Cache Read Flow Chart 17. Added DQ6 Toggle Bit Information on Chapter 3.13 18. Added ISB information on DDP 19. Revised Reset Parameter descriptions 20. Added Asynchronous Write timing diagram 21. Added RDY information on Warm Reset Timing diagram 22. Added information on Data Protection Timing During Power Down 23. Added Toggle Bit Timing in Asynchronous Read timing diagram 24. Revised Interrupt pin rise and falling slope graph 25. Added restriction on address register setting on Dual Operations 26. Added restriction on address register setting on Cache Read Operation 27. Added Technical Note 1.1 Revision History |
Аналогичный номер детали - KFM1G16Q2M-DED6 |
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Аналогичное описание - KFM1G16Q2M-DED6 |
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